The 8085 Microprocessor
The Intel 8085 is an 8-bit microprocessor widely used for educational purposes. It has a simple architecture that demonstrates fundamental concepts of microprocessor design, instruction execution, and low-level programming.
Architecture
The 8085 has an 8-bit data bus, 16-bit address bus (64KB addressable memory), and operates at up to 5 MHz. Internal components include the ALU, timing and control unit, instruction register, program counter (PC), stack pointer (SP), and registers: A (accumulator), B, C, D, E, H, L (general purpose, can be paired as BC, DE, HL).
Pin Diagram
The 8085 has 40 pins. Key pins: AD₀–AD₇ (multiplexed address/data), A₈–A₁₅ (higher address), ALE (Address Latch Enable), RD' and WR' (read/write control), IO/M' (I/O or memory), INTR and RST interrupts, CLK, RESET, HOLD/HLDA (DMA), SID/SOD (serial I/O).
Instruction Set
The 8085 has 246 instructions classified by function: data transfer (MOV, MVI, LDA, STA, LXI), arithmetic (ADD, ADI, SUB, INR, DCR, DAD), logical (ANA, ORI, XRA, CMP, RLC, RAR), branching (JMP, JZ, JNZ, CALL, RET), and machine control (HLT, NOP, EI, DI). Instructions are 1, 2, or 3 bytes.
Addressing Modes
The 8085 supports: immediate (MVI A, 32H), register (MOV A, B), direct (LDA 2050H), register indirect (MOV A, M — where M is memory at HL), and implicit (CMA — operates on accumulator implicitly).
Timing and Machine Cycles
Each instruction takes one or more machine cycles (opcode fetch, memory read/write, I/O read/write). Each machine cycle has 3–6 T-states (clock cycles). The opcode fetch cycle takes 4 T-states. Understanding timing diagrams is essential for interfacing.
Interrupts
The 8085 has five interrupts: TRAP (non-maskable, highest priority), RST 7.5, RST 6.5, RST 5.5 (maskable, vectored), and INTR (maskable, non-vectored, lowest priority). EI enables and DI disables maskable interrupts. SIM instruction sets interrupt masks.
Summary
The 8085 microprocessor provides a clear introduction to processor architecture, instruction sets, timing, and interrupt handling. These concepts scale to understanding modern processors.