Chapter 7: Processor Logic Design
Introduction to Processor Architecture
A processor is a digital system that executes instructions, performing computation and control. Understanding how processors are designed—from basic logic components to complete instruction execution—is the foundation of computer architecture. This chapter covers the essential building blocks: organization, bus architecture, ALU design, and the arithmetic/logic circuits that implement processor operations.
1. Basic Processor Organization
Fetch-Execute Cycle
A processor operates in cycles: fetch an instruction from memory, decode it to understand what operation to perform, execute the operation, and store results. These steps are fundamental to all processors, from simple microcontrollers to complex modern CPUs.
Main Components
The processor contains several key components: registers (for fast storage), the ALU (arithmetic/logic unit) for computation, the control unit (for directing operations), memory interface (for instruction and data access), and buses (for moving data between components). Each component plays a specific role in instruction execution.
2. Bus Architecture
Data Bus
The data bus carries data between the processor, memory, and input/output devices. An n-bit processor has an n-bit data bus (16-bit, 32-bit, 64-bit, etc.). Wider buses allow more data to move simultaneously, increasing throughput.
Address Bus
The address bus specifies which memory location to access. With m address lines, the processor can address 2^m memory locations. A 16-bit address bus enables access to 64KB of memory; 32-bit allows 4GB.
Control Bus
The control bus carries control signals: read/write (is this a read or write operation?), interrupt signals, clock, reset, and other synchronization signals. These coordinate all processor operations.
Bus Timing and Protocols
Memory and I/O devices respond at different speeds. Bus protocols define handshakes: the processor asserts an address, memory asserts ready when data is available, then data is transferred. Synchronizing different components on the bus is critical for correct operation.
3. Arithmetic Logic Unit (ALU) Design
ALU Function
The ALU performs arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR). An instruction specifies which operation via an operation code (opcode). The ALU receives two operands, performs the operation, and outputs the result and status flags.
ALU Inputs and Outputs
Typical ALU has two n-bit operand inputs, an operation select input, an n-bit result output, and flag outputs (carry, zero, sign, overflow). The flag outputs indicate important conditions: was there a carry? Is the result zero? Is it negative? Did overflow occur (arithmetic error)?
Building ALU Circuits
An ALU can be constructed hierarchically: for each bit position, create a logic cell performing the selected operation, then combine across all bit positions. Multiplexers select which operation to perform. Carry and borrow logic chains through the stages for arithmetic operations.
4. Implementing Arithmetic Operations
Binary Addition
We've seen adders before: full adders cascaded to add multi-bit numbers. The key point here: in a processor ALU, the adder is just one operation. A multiplexer or control logic selects the adder when an add instruction arrives.
Binary Subtraction
Subtraction uses 2's complement addition. A - B is computed as A + 2's complement of B. The 2's complement is generated by inverting B and adding 1 (via the carry-in of the first adder stage).
Multiplication
Hardware multiplication can be done by repeated addition (slow) or using array multipliers (faster but more area). Modern ALUs typically implement multiplication using specialized circuits or by calling dedicated multiply units.
Division
Division is complex in hardware and typically uses repeated subtraction or more sophisticated algorithms. Some processors implement division in the ALU; others use firmware (microcode) or shift the operation to software.
5. Logical Operations
Bit-wise Operations
AND, OR, XOR, NOT are performed bit-by-bit. Implementation is trivial: for each bit position, apply the selected logical operation independently. These operations are used for bit manipulation, masking, and testing.
Shift Operations
Shift left (multiply by 2) and shift right (divide by 2) are fundamental operations. Barrel shifters can shift by any amount in one cycle. Shift operations are used for:bit manipulation, converting between different number formats, and implementing multiply/divide by powers of 2.
Rotate Operations
Rotate is like shift but the bits that fall off one end reappear at the other. Rotate left and right are useful for circular operations and certain cryptographic algorithms.
6. Status Flags and Condition Codes
Flag Register
The processor maintains a flags register with bits for important status conditions: Zero flag (Z) is set if result is zero. Carry flag (C) is set if arithmetic produced a carry. Sign flag (S) is set if the result is negative (MSB=1). Overflow flag (V) is set if signed arithmetic overflowed.
Using Flags for Conditional Execution
Branch instructions test flags: "jump if zero," "jump if carry," etc. This allows the program to make decisions based on arithmetic results, implementing conditional logic at the processor level.
7. Control Unit and Instruction Decoding
Instruction Format
An instruction specifies the operation and operands. Common format: opcode (what operation) + addressing mode (where to find operands) + operand addresses. The control unit decodes this instruction and generates control signals for all processor components.
Control Signals
For each instruction, the control unit must: select which registers to read, route their data to the ALU, select the ALU operation, route the result to the correct register or memory location, and update the program counter. Each instruction type generates a specific sequence of control signals.
8. Register File Design
Register Organization
A register file is a small, fast memory containing the processor's general-purpose and special-purpose registers. With m registers, an instruction needs log2(m) bits to specify which register. Multiple read ports allow simultaneous access to different registers (needed for most ALU operations).
Register Selection Logic
For each of the processor's registers, selection logic determines whether to read from it, write to it, or ignore it based on the instruction. Multiplexers select which register's data goes to the ALU; decoders enable writes to the selected register.
9. Memory Interface
Load and Store Instructions
Load reads data from memory into a register. Store writes register data to memory. Both require address calculation, memory access timing, and data routing. The processor must place the address on the address bus, set read/write control, wait for memory response, and transfer data.
Timing Synchronization
Memory responds slower than the processor operates. The processor must wait for memory to fetch or store data. Wait states insert idle clock cycles until memory is ready. More sophisticated systems use caches to reduce memory wait time.
10. Pipelining and Parallel Processing (Introduction)
Instruction Pipelining
Instead of finishing one instruction completely before starting the next, modern processors overlap instruction execution: while one instruction is in the ALU, another is being decoded, and a third is being fetched from memory. Pipelining increases throughput dramatically but adds complexity (hazards, branch penalties).
Conclusion
Processor design integrates all concepts from previous chapters: combinational logic (ALU, multiplexers), sequential logic (registers, state machines), and data flow control (buses, memory interface). Understanding these components and how they interact is the foundation for computer architecture and system design. Modern processors are vastly more complex, but the fundamental principles remain: fetch instructions, decode them, execute operations on data, and store results.