Chapter 5: Sequential Logic and Flip-Flops
Introduction to Sequential Circuits
Unlike combinational circuits where outputs depend only on current inputs, sequential circuits have memory—outputs depend on both current inputs and past history (state). This memory is implemented using flip-flops, which are bistable devices that can store one bit of information. Understanding flip-flops and sequential design is fundamental to building practical digital systems like counters, shift registers, and state machines.
1. Latches vs. Flip-Flops
SR Latch (Set-Reset)
The SR latch is the basic memory element, made from two cross-coupled NOR gates (or NAND gates). It has two inputs (Set and Reset) and two outputs (Q and Q'). When S=1 and R=0, Q becomes 1 (set). When S=0 and R=1, Q becomes 0 (reset). When both are 0, Q maintains its previous state (memory). The forbidden state S=1, R=1 should be avoided as it creates an undefined state.
Flip-Flops vs. Latches
A latch is level-triggered: it responds to input changes as long as the enable signal is high. A flip-flop is edge-triggered: it responds only at the clock edge (rising or falling). This edge-triggering provides better synchronization in digital systems, as all state changes occur at precise clock moments.
2. SR Flip-Flop
Synchronous SR Flip-Flop
The SR flip-flop adds a clock input to the SR latch. State changes occur only when the clock edge arrives. Between clock edges, S and R inputs are ignored, preventing metastability issues. The characteristic equation: Q(t+1) = S + R'Q(t), where S and R should not both be 1.
3. D Flip-Flop (Data)
Concept and Advantage
The D flip-flop eliminates the S=R=1 problem by combining S and R through an inverter: R is always the complement of S. The single input D (Data) determines the next state: when the clock edge arrives, Q becomes equal to D. This makes D flip-flops ideal for straightforward data capture and storage.
Master-Slave Structure
To prevent setup/hold time issues, D flip-flops are often constructed as master-slave pairs. The master latch responds to the clock high phase, the slave to the clock low phase. This two-stage structure ensures stable transitions and prevents race conditions.
4. JK Flip-Flop
Function and Advantage
The JK flip-flop has two inputs (J and K) and eliminates the forbidden state problem of SR. Truth table: JK=00 (no change), JK=01 (reset to 0), JK=10 (set to 1), JK=11 (toggle—flip to opposite state). The characteristic equation: Q(t+1) = JQ'(t) + K'Q(t).
Toggle Operation
The toggle operation (JK=11) is unique to JK flip-flops and is valuable for designing counters and frequency dividers. When J=K=1, the flip-flop changes state with every clock edge.
5. T Flip-Flop (Toggle)
Concept
The T flip-flop is essentially a JK with J and K tied together. A single input T controls behavior: T=0 (no change), T=1 (toggle). The characteristic equation: Q(t+1) = TQ'(t) + T'Q(t). T flip-flops are perfect for building binary counters because they naturally divide frequency by 2.
6. State Tables and State Diagrams
State Table
A state table documents flip-flop behavior: inputs, current state, next state, and outputs. It's the foundation for analyzing and designing sequential circuits.
State Diagram
A state diagram graphically shows states (circles) and transitions (arrows). Input conditions that trigger transitions are labeled on the arrows. State diagrams help visualize circuit behavior and are essential for designing state machines.
7. Design of Sequential Circuits
Step-by-Step Design Process
Start with a problem description and create a state diagram. Assign binary codes to each state, then use state tables to determine flip-flop inputs for each transition. Derive Boolean expressions for flip-flop inputs and outputs, then implement with gates and flip-flops.
Choosing Flip-Flop Types
Different flip-flop types suit different applications. D flip-flops are ideal for simple data storage and shift registers. JK flip-flops are versatile and good for counters. T flip-flops are specialized for frequency division and binary counters.
8. Timing Specifications
Setup Time
The setup time is the minimum duration that input data must be stable before the clock edge arrives. Violating setup time can cause metastability (unpredictable output).
Hold Time
The hold time is the minimum duration that input data must remain stable after the clock edge. Again, violation causes metastability.
Propagation Delay
After the clock edge, outputs don't change instantly. The propagation delay is the maximum time before outputs reach their final values. This parameter is critical for calculating maximum operating frequency.
9. Metastability and Clock Domain Crossing
What is Metastability?
When a flip-flop input changes near the clock edge (violating setup/hold times), the flip-flop enters a metastable state where output voltage is between 0 and 1. Eventually it resolves to 0 or 1, but the outcome is unpredictable, and it may take longer than normal to settle.
Clock Domain Crossing
When data crosses from one clock domain to another, metastability is unavoidable unless there's a synchronizer. A synchronizer is a chain of flip-flops that reduces metastability probability to acceptable levels (typically 2-3 flip-flops are sufficient).
Conclusion
Sequential circuits add memory and state to digital systems. Flip-flops are the fundamental building blocks, available in several types (SR, D, JK, T) suited to different applications. Understanding state diagrams, state tables, and design procedures is essential for creating counters, shift registers, and state machines. Timing specifications and metastability are practical considerations that separates theoretical design from reliable implementation.